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? semiconductor components industries, llc, 2002 february, 2002 rev. 10 1 publication order number: mc33364/d mc33364 critical conduction greenline ? smps controller the mc33364 series are variable frequency smps controllers that operate in the critical conduction mode. they are optimized for high density power supplies requiring minimum board area, reduced component count, and low power dissipation. integration of the high voltage startup saves approximately 0.7 w of power compared to the value of the resistor bootstrapped circuits. each mc33364 features an onboard reference, uvlo function, a watchdog timer to initiate output switching, a zero current detector to ensure critical conduction operation, a current sensing comparator, leading edge blanking, a cmos driver and cyclebycycle current limiting. the mc33364d1 has an internal 126 khz frequency clamp. the mc33364d2 is available without an internal frequency clamp. the mc33364d has an internal 126 khz frequency clamp which is pinned out, so that the designer can adjust the clamp frequency by connecting appropriate values of resistance. ? lossless offline startup ? leading edge blanking for noise immunity ? watchdog timer to initiate switching ? operating temperature range 25 to +125 c ? shutdown capability ? over temperature protection ? optional/adjustable frequency clamp to limit emi startup ref restart delay watchdog timer frequency clamp thermal shutdown line gate pgnd cs fc fb vref zcd vcc uvlo uvlo zcd current leb vcc r r s q emi filter 85 to 265 vac agnd + sense so16 d suffix case 751b so8 d1, d2 suffix case 751 16 1 8 1 pin connections mc33364d1 mc33364d2 mc33364d 18 7 6 5 2 3 4 (top view) zero current current sense voltage fb line v ref gnd gate drive v cc 116 13 12 11 10 9 2 3 4 5 6 7 8 (top view) zero current n/c current sense v ref n/c freq clamp line a gnd voltage fb n/c p gnd gate drive v cc n/c see detailed ordering and shipping information in the package dimensions section on page 14 of this data sheet. ordering information 1 16 mc33364d awlyww m64dx alyw 1 8 marking diagrams x = 1 or 2 a = assembly location wl, l = wafer lot yy, y = year ww, w = work week http://onsemi.com
mc33364 http://onsemi.com 2 figure 1. representative block diagram this device contains 335 active transistors. startup reference restart delay watchdog timer frequency clamp thermal shutdown level sna line gate pgnd cs fc fb vref zcd vcc vcc uvlo ref uvlo zcd vref buffer 4.7 15 / 7.6 10v 1.2/1.0 1.25v 45k 15k 4k 10v 0.1v 2v current sense leb vcc 5k r r s q agnd timing diagrams load current voltage fb zcd gate drive 10v 0v -0.7v normal load no load programmed minimum off time (fc) leb drain current
mc33364 http://onsemi.com 3 pin description pin function description 1 (1) zero current detect the zcd pin ensures critical conduction mode. zcd monitors the voltage on the auxiliary winding, during the demagnetization phase of the transformer, comparing it to an internal reference. the zcd sets the latch for the output driver. 3 (2) current sense the current sense pin monitors the current in the power switch by measuring the voltage across a resistor. leading edge blanking is utilized to prevent false triggering. the voltage is compared to a resistor divider connected to the voltage feedback pin. a 110 mv voltage offset is applied to compensate the natural optocoupler saturation voltage. 4 (3) voltage feedback the voltage feedback pin is typically connected to the collector of the optocoupler for feedback from the isolated secondary output. the feedback is connected to the v ref pin via a 5 k resistor providing bias for the external optocoupler. 6 (4) v ref the v ref pin is a buffered internal 5.0 v reference with undervoltage lockout. 8 (na) frequency clamp the frequency clamp pin ensures a minimum offtime value, typically 6.9 s. it prevents the mosfet from restarting within a fixed (33364d1) or adjustable (33364d) delay. the minimum offtime is disabled in the 33364d2. therefore the maximum switching frequency cannot exceed 1/(t on + t offmin ). 9 (5) a gnd this pin is the ground for the internal circuitry excluding the gate drive stage. 10 (5) p gnd this pin is the ground for the gate drive stage. 11 (6) gate drive the gate drive is the output to drive the gate of the power mosfet. 12 (7) v cc provides the voltage for all internal circuitry including the gate drive stage and v ref . this pin has undervoltage lockout with hysteresis. 16 (8) line the line pin provides the initial power to the v cc pins. internally the line pin is a high voltage current source, eliminating the need for an external startup network. for further information please refer to the following application notes; an1594: critical conduction mode, flyback switching power supply using the mc33364. an1681: how to keep a flyback switchmode power supply stable with a criticalmode controller. maximum ratings (t a = 25 c, unless otherwise noted.) rating symbol value unit power supply voltage (operating) v cc 16 v line voltage v line 700 v current sense, compensation, voltage feedback, restart delay and zero current input voltage v in1 1.0 to +10 v zero current detect input i in 5.0 ma restart diode current i in 5.0 ma power dissipation and thermal characteristics d1 and d2 suffix, plastic package case 751 maximum power dissipation @ t a = 70 c p d 450 mw thermal resistance, junctiontoair r q ja 178 c/w d suffix, plastic package case 751b05 maximum power dissipation @ t a = 70 c p d 550 mw thermal resistance, junctiontoair r q ja 145 c/w operating junction temperature t j 150 c operating ambient temperature t a 25 to +125 c storage temperature range t stg 55 to +150 c note: esd data available upon request.
mc33364 http://onsemi.com 4 electrical characteristics (v cc = 12 v, for typical values t a = 25 c, for min/max values t j = 25 to 125 c) characteristic symbol min typ max unit voltage reference reference output voltage (i out = 0 ma, t j = 25 c) v ref 4.90 5.05 5.20 v line regulation (v cc = 10 v to 20 v) reg line 2.0 50 mv load regulation (i out = 0 ma to 5.0 ma) reg load 0.3 50 mv maximum v ref output current i o 5 ma reference undervoltage lockout threshold v th 4.5 v zero current detector input threshold voltage (v in decreasing) v th 0.9 1.0 1.1 v hysteresis (v in decreasing) v h 200 mv input clamp voltage v high state (i det = 3.0 ma) v ih 9.0 10.33 12 low state (i det = 3.0 ma) v il 1.1 0.75 0.5 current sense comparator input bias current (v cs = 0 to 2.0 v) i ib 0.5 0.02 0.5 m a built in offset v io 50 108 170 mv feedback pin input range v fb 1.1 1.24 1.4 v feedback pin to output delay t dly 100 232 400 ns drive output source resistance (drive = 0 v, v gate = v cc 1.0 v) r oh 10 36 70 w sink resistance (drive = v cc , v gate = 1.0 v) r ol 5 11 25 w output voltage rise time (25% 75%) (c l = 1.0 nf) t r 67 150 ns output voltage fall time (75% 25%) (c l = 1.0 nf) t f 28 50 ns output voltage in undervoltage (v cc = 7.0 v, i sink = 1.0 ma) v o(uv) 0.01 0.03 v leading edge blanking delay to current sense comparator input t phl(in/out) 250 ns (v fb = 2.0 v, v cs = 0 v to 4.0 v step, c l = 1.0 nf) timer watchdog timer t dly 200 360 700 m s undervoltage lockout startup threshold (v cc increasing) v th(on) 14 15 16 v minimum operating voltage after turnon (v cc decreasing) v shutdown 6.5 7.6 8.5 v frequency clamp internal fc function (pin open) f max 104 126 145 khz internal fc function (pin grounded) f max 400 564 800 khz frequency clamp input threshold v th(fc) 1.89 1.95 2.01 v frequency clamp control current range (sink) i control 30 70 110 m a dead time (fc pin = 1.7 v) t d 3.5 5.0 6.5 m s total device line startup current (v line = 50 v) (v cc = v th(on) 1.0 v) i line 5.0 8.5 12 ma restart delay time t dly 100 ms line pin leakage (v line = 500 v) i line 0.5 32 70 m a line startup current (v cc = 0 v, v line = 50 v) i line 6.0 10 12 ma v cc dynamic operating current (50 khz, c l = 1.0 nf) i cc 1.5 2.75 4.5 ma v cc off state consumption (v cc = 11 v) i cc off 300 544 800 m a
mc33364 http://onsemi.com 5 -100 t d , programmed dead time ( sec) i fc , frequency clamp source / sink current ( m a) 0.0 -60 0 40 100 m -55 500 t dly , watchdog time delay ( s) t a , ambient temperature ( c) m 450 400 350 300 -25 0 25 50 75 100 125 v cc = 15 v figure 2. drive output waveform figure 3. watchdog timer delay versus temperature 25 output voltage (v) 5.0 m s/div 20 15 10 0 -5.0 4.0 6.0 i cc , supply current (ma) v cc , supply voltage (v) circuit of figure 8 t a = 25 c 4.0 2.0 0 6.0 8.0 10 12 14 16 figure 4. supply current versus supply voltage 0.01 1000 r ja(t) , thermal resistance t, time (s) q junction-to-air ( c/w) 100 10 0.1 1.0 10 100 figure 5. transient thermal resistance d suffix 16 pin soic figure 6. dead time versus frequency clamp source / sink current d suffix 16 pin soic t a = 25 c v cc = 14 v 5.0 10 20 25 v cc = 14 v c l = 1000 pf t a = 25 c 30 5.0 15 -80 -40 20 60 -20 80 0 current sense voltage feedback voltage -0.4 1.0 2.5 3.5 5.0 figure 7. feedback voltage versus current sense voltage -0.2 0 0.4 0.6 0.2 0.5 1.5 3.0 4.0 2.0 4.5 0.8 1.0 1.2 1.4 6.0 5.5 d suffix 16 pin soic t a = 25 c v cc = 15 v
mc33364 http://onsemi.com 6 functional description introduction with the goal of reducing the size and cost of offline power supplies, there is an ever increasing demand for an economical method of obtaining a regulated galvanically isolated dc output voltage using a control which operates directly from the ac line. this data sheet describes a monolithic control ic that was specifically designed for power supply control with a minimal number of external components. it offers the designer a simple cost effective solution to obtain the benefits of offline power regulation. figure 8. functional block diagram startup reference restart delay watchdog timer frequency clamp thermal shutdown line gate pgnd cs fc fb vref zcd vcc vcc uvlo ref uvlo zcd vref buffer 4.7 15 / 7.6 10v 1.2/1.0 1.25v 45k 15k 4k 10v 0.1v 2v current sense leb vcc 5k r r s q emi filter 85 to 265 vac c1 10 m f 400v d1 1n4006 mtd1n60 q1 t1 r4 470 (optional) r10 14 k r8 430 c8 330 pf 6.0 v 2.0 a c7 10 nf c4 1 m f 1 2 4 5 u2 tl431 2 1 3 d5 1n4934 d6 mur160 d8 mbr340 r1 56 r6 47 k r9 39 k r11 10 k agnd d2 d3 d4 r7 2.2 c3 20 m f c10 0.1 m f r5 47 k c5 300 m f u3 moc8102 + note: frequency clamp and agnd applicable on d version only. r2 22 k
mc33364 http://onsemi.com 7 operating description the mc33364 contains many of the building blocks and protection features that are employed in modern high performance current mode power supply controllers. referring to the block diagram in figure 8, note that this device does not contain an oscillator. a description of each of the functional blocks is given below. zero current detector the mc33364 operates as a critical conduction current mode controller, whereby the output switch conduction is initiated by the zero current detector pin and terminated when the peak inductor current reaches the programmed threshold level. the zcd pin indirectly monitors the inductor current by sensing the auxiliary winding voltage. when the voltage falls below the set threshold, 1.0 volt, the comparator resets the latch to turn on the mosfet. there is 200 mv of hysteresis built into the comparator for noise immunity and to prevent false tripping the zcd pin is internally protected by a 10 volt and 0.7 volt clamp. an external resistor is necessary to limit the input current to 2 ma to protect the clamp. since the mc33364 implements the zcd pin, the smps circuit has the following benefits: 1. a less expensive rectifier can be used on the output windings because of the zero current switching which naturally softens the diode turnoff. 2. the second benefit is the peak drain current which is limited to twice the average input current. by combining the zcd series resistor with the pin capacitance, a drainsource valley switching can be implemented, further reducing the turnon losses and the emi disturbances. 3. by preventing the smps from entering the continuous conduction mode (ccm), the mc33364 forces the system to stay a firstorder device (in the lower frequency range) in any operating condition (output short, startup, low mains). the feedback compensation network is thus considerably simplified. current sense and feedback inputs the current sense pin and the feedback pin are linked internally in the device via the current sense comparator. the output of the comparator is connected to the set of the rs latch, which turns the external mosfet off. the current sense operates by using a resistor, connected between the source of the mosfet and ground, to convert the current through the inductor to a voltage. leading edge blanking is implemented to prevent false triggering due to parasitics. the current sense voltage is level shifted up by 0.1 volt into the noninverting input of the comparator. this offset accounts for the optocoupler vcesat and allows the dutycycle to be zero. the maximum peak switch current is 1.15v (the maximum voltage at the inverting input, 1.25 volts, minus 0.1 volt, the level shift) divided by the external current sense resistance. the current sense input to drive output propagation delay is 232 nsec typically. the feedback pin is internally pulled up with a 5 kohm resistor from the 5.0 volt vref pin. the feedback pin uses a resistor divider to proportionally adjust the voltage into the inverting input of the comparator. the inverting input also has a 1.25 volt clamp. typically the feedback pin is connected to the collector of the optocoupler. timer a watchdog timer function was added to the ic to eliminate the need for an external oscillator when used in stand alone applications. the timer provides a means to automatically start or restart the preconverter if the drive output has been off for more than 410 microseconds after the inductor current reaches zero. this timeout thus ensures the ic will restart when the demagnetization signal is lower than the internal zcd 1v threshold or has simply been lost. undervoltage lockout the mc33364 has a hysteretic uvlo associated with the v cc pin. during startup, v cc must rise to 15 volts to turn off the startup circuit associated with the line pin and to enable the output drivers. the voltage at v cc must remain above 7.6 volts for the part to remain operational. internal reference the mc33364 has an internal buffered 5.0 volt reference. the reference requires a 0.1 m f bypass capacitor for noise immunity. the reference is capable of sourcing 10 ma typically. the reference contains an independant uvlo which will disable the output drive circuitry. startup circuit and restart delay a high voltage startup circuit is contained within the mc33364 eliminating the need for external components. the internal startup circuit operates as a constant current source to charge up the bypass capacitor on the v cc pin. the startup circuitry is controlled by the restart delay circuitry. the threshold levels of the turn on and turn off are below 4.5 volts and above 15 volts, respectively, as measured on the v cc pin. a restart delay function is provided to allow hiccup mode fault protection in case of a short circuit condition and to prevent the smps from repeatedly trying to restart after the input line voltage has been removed. during a short circuit, the restart delay prevents excessive power dissipation in the primary side of the smps and allows time for the output to reset the fault condition. the restart delay time is approximately 100 msec. output switching frequency clamp in normal operation, the mc33364 operates the flyback transformer in the critical conduction mode. the ccm is defined by the transformer ramping to a peak current value, ramping down to zero, then immediately ramping positive again. the peak current is programmed by the current sense resistor and is compared with a divided down voltage from
mc33364 http://onsemi.com 8 the feedback pin. when the output is reduced from full load to standby or no load, the switching frequency can increase dramatically to hundreds of kilohertz. due to emi regulations above 150 khz, the frequency clamp on the mc33364d and mc33364d1 will limit the upper frequency by inserting a minimum off time. the frequency of a switching regulator is determined by f = 1/(t on + t off ). during light load and no load conditions, t off is the reset time of the transformer plus dead time. at no load conditions, t on is approximately the leb and t off is the programmed minimum offtime. with the addition of logic delay times, the maximum frequency when the fc pin floats is 126 khz nominally. the frequency clamp inserts a minimum offtime immediately after the driving signal goes low. if the zcd signal comes within this minimum offtime, the information is ignored until the minimum offtime expires. by forcing the minimum offtime, the transformer will operate in the discontinuous mode. the next coming zcd signal starts the latch. the mc33364 is available in three versions: mc33364d1: the internal minimum offtime is fixed at 6.9 m sec typically mc33364d2: there is no internal minimum offtime mc33364d: the internal minimum offtime can be either lengthened, shortened or eliminated by biasing the appropriate pin the fc pin contains a 4.0 kohm series resistor into the noninverting input of a comparator. the noninverting input has a 10 volt clamp to limit overvoltage. refer to figure 9 for a detailed circuit of the frequency clamp. figure 9. simplified frequency clamp circuit frequency clamp gate drive signal fc output to pwm or gate 4.0 k 10 pf 2.0 v 5.0 v 3.0 m a 2.0 v r vcc (optional) off time increase r gnd (optional) off time decrease note: for proper operation, use either r vcc or r gnd or let the pin float. the mc33364d has a frequency clamp pin which can vary the maximum frequency. if the fc pin floats, the minimum offtime is fixed at 6.9 m sec typically. if the fc pin is grounded, the clamp is disabled. sinking or sourcing a current up to 100 m a into the fc pin will vary the maximum frequency (see figure 6). however, we do not recommend exceeding 80 m a because the high ddt/difc would not ensure a stable operation. output the ic contains a cmos output driver specifically designed for direct drive of power mosfets. the drive output typical rise and fall time is 50 ns with a 1.0 nf load. unbalanced source and sink capability eliminates the need for an external resistor between the ic drive output and the gate of the external mosfet. additional internal circuitry has been added to keep the drive output in a sinking mode whenever the uvlo is active. this characteristic eliminates the need for an external gate pulldown resistor.
mc33364 http://onsemi.com 9 application information design example design an offline flyback converter according to the following requirements: output power: 12 w output: 6.0 v @ 2 amperes input voltage range: 90 vac 270 vac, 50/60 hz the operation for the circuit shown in figure 8 is as follows: the rectifier bridge d1d4 and the capacitor c1 convert the ac line voltage to dc. this voltage supplies the primary winding of the transformer t1 and the startup circuit in u1 through the line pin. the primary current loop is closed by the transformer's primary winding, the tmos switch q1 and the current sense resistor r7. the resistors r5, r6, diode d6 and capacitor c4 create a snubber clamping network that protects q1 from spikes on the primary winding. the network consisting of capacitor c3, diode d5 and resistor r1 provides a v cc supply voltage for u1 from the auxiliary winding of the transformer. the resistor r1 makes v cc more stable and resistant to noise. the resistor r2 reduces the current flow through the internal clamping and protection zener diode of the zero crossing detector (zcd) within u1. c3 is the decoupling capacitor of the supply voltage. the resistor r3 can provide additional bias current for the optoisolator's transistor. the diode d8 and the capacitor c5 rectify and filter the output voltage. the tl431, a programmable voltage reference, drives the primary side of the optoisolator to provide isolated feedback to the mc33364. the resistor divider consisting of r10 and r11 program the voltage of the tl431. the resistor r9 and the capacitors c7 and c8 provide frequency compensation of the feedback loop. resistor r8 provides a current limit for the opto coupler and the tl431. since the critical conduction mode converter is a variable frequency system, the mc33364 has a builtin special block to reduce switching frequency in the no load condition. this block is named the ofrequency clampo block. mc33364 used in the design example has an internal frequency clamp set to 126 khz. however, optional versions with a disabled or variable frequency clamp are available. the frequency clamp works as follows: the clamp controls the part of the switching cycle when the mosfet switch is turned off. if this oofftimeo (determined by the reset time of the transformer's core) is too short, then the frequency clamp does not allow the switch to turnon again until the defined frequency clamp time is reached (i.e., the frequency clamp will insert a dead time). there are several advantages of the mc33364's startup circuit. the startup circuit includes a special high voltage switch that controls the path between the rectified line voltage and the v cc supply capacitor to charge that capacitor by a limited current when the power is applied to the input. after a few switching cycles the ic is supplied from the transformer's auxiliary winding. after v cc reaches the undervoltage lockout threshold value, the startup switch is turned off by the undervoltage and the overvoltage control circuit. because the power supply can be shorted on the output, causing the auxiliary voltage to be zero, the mc33364 will periodically start its startup block. this mode is named ohiccup modeo. during this mode the temperature of the chip rises but remains protected by the thermal shutdown block. during the power supply's normal operation, the high voltage internal mosfet is turned off, preventing wasted power, and thereby, allowing greater circuit efficiency. since a bridge rectifier is used, the resulting minimum and maximum dc input voltages can be calculated: v in(min) dc 2 xv in(min) ac 2
( 90 vac ) 127 v v in( ax) dc 2 xv in( ax) ac 2
( 270 vac ) 382 v the maximum average input current is: i in p out nv in(min) 12 w 0.8 ( 127 v ) 0.118 a where n = estimated circuit efficiency. a tmos switch with 600 v avalanche breakdown voltage is used. the voltage on the switch's drain consists of the input voltage and the flyback voltage of the transformer's primary winding. there is a ringing on the rising edge's top of the flyback voltage due to the leakage inductance of the transformer. this ringing is clamped by the rcd network. design this clamped wave for an amplitude of 50 v below the avalanche breakdown of the tmos device. add another 50 v to allow a safety margin for the mosfet. then a suitable value of the flyback voltage may be calculated: v flbk v tmos v in(max) 100 v 600 v 382 v 100 v 118 v since this value is very close to the v in(min) , set: v flbk v in(min) 127 v the v flbk value of the duty cycle is given by: max v flbk v flbk v in(min) 127 v [ 127 v 127 v ] 0.5 the maximum input primary peak current: i ppk 2i in max 2.0 ( 0.118 a ) 0.5 0.472 a choose the desired minimum frequency f min of operation to be 70 khz. after reviewing the core sizing information provided by a core manufacturer, a ee core of size about 20 mm was chosen. siemens' n67 magnetic material is used, which corresponds to a philips 3c85 or tdk pc40 material.
mc33364 http://onsemi.com 10 the primary inductance value is given by: l p max v in(min) i ppk
f min
0.5 ( 127 v ) ( 0.472 a )( 70 khz ) 1.92 mh the manufacturer recommends for that magnetic core a maximum operating flux density of: b max 0.2 t the crosssectional area a c of the ef20 core is: a c 33.5 mm 2 the operating flux density is given by: b max l p i ppk n p a c from this equation the number of turns of the primary winding can be derived: n p l p i ppk b max a c the a l factor is determined by: a l l p n 2 p l p b max a c
2 l p i ppk
2 0.2 t
33.5 e6 m 2
2 .00192 h
( 0.472 a ) 2 105 nh from the manufacturer`s catalogue recommendation the core with an a l of 100 nh is selected. the desired number of turns of the primary winding is: n p l p a l
1 2 ( 0.00192 h ) ( 100 nh ) 1 2 139 turns the number of turns needed by the 6.0 v secondary is (assuming a schottky rectifier is used): n s v s v fwd
1 max
n p max v in(min)
6.0 v 0.3 v
1 0.5
139 0.5 127 v
7 turns the auxiliary winding to power the control ic is 16 v and its number of turns is given by: naux (v aux v fwd )(1 max)n p max(v in(min) ) (16 v 0.9 v)(1 0.5)139 [0.5(127 v)] 19 turns the approximate value of rectifier capacitance needed is: c1 t off (i in ) v ripple (5 m sec)(0.118 a) 50 v 11.8 f where the minimum ripple frequency is 2 times the 50 hz line frequency and t off , the discharge time of c1 during the haversine cycle, is assumed to be half the cycle period. because we have a variable frequency system, all the calculations for the value of the output filter capacitors will be done at the lowest frequency, since the ripple voltage will be greatest at this frequency. when selecting the output capacitor select a capacitor with low esr to minimize ripple from the current ripple. the approximate equation for the output capacitance value is given by: c5 i out (f min )(v rip ) 2a (70 khz)(0.1 v) 286 f determining the value of the current sense resistor (r7), one uses the peak current in the predesign consideration. since within the ic there is a limitation of the voltage for the current sensing, which is set to 1.2 v, the design of the current sense resistor is simply given by: r7 v cs i ppk 1.2 v 0.472 a 2.54 2.2 the error amplifier function is provided by a tl431 on the secondary, connected to the primary side via an optoisolator, the moc8102. the voltage of the optoisolator collector node sets the peak current flowing through the power switch during each cycle. this pin will be connected to the feedback pin of the mc33364, which will directly set the peak current. starting on the secondary side of the power supply, assign the sense current through the voltagesensing resistor divider to be approximately 0.25 ma. one can immediately calculate the value of the lower and upper resistor: r lower r11 v ref (tl431) i div 2.5 v 0.25 ma 10 k r upper r10 v out v ref (tl431) i div 6.0 v 2.5v 0.25 ma 14 k the value of the resistor that would provide the bias current through the optoisolator and the tl431 is set by the minimum operating current requirements of the tl431. this current is minimum 1.0 ma. assign the maximum current through the branch to be 5 ma. that makes the bias resistor value equal to:
mc33364 http://onsemi.com 11 r bias r s v out [v ref (tl431) v led ] i led 6.0 v [2.5v 1.4v] 5.0 ma 420 430 the moc8102 has a typical current transfer ratio (ctr) of 100% with 25% tolerance. when the tl431 is fullon, 5 ma will be drawn from the transistor within the moc8102. the transistor should be in saturated state at that time, so its collector resistor must be r collector v ref v sat i led 5.0 v 0.3 v 5.0 ma 940 since a resistor of 5.0 k is internally connected from the reference voltage to the feedback pin of the mc33364, the external resistor can have a higher value r ext r3 (r int )(r collector ) (r int ) (r collector ) (5.0 k)(940) 5.0 k 940 1157 1200 this completes the design of the voltage feedback circuit. in no load condition there is only a current flowing through the optoisolator diode and the voltage sense divider on the secondary side. the load at that condition is given by: r noload v out (i led i div ) 6.0 v (5.0 ma 0.25 ma) 1143 the output filter pole at no load is: f pn 1 (2 r noload c out ) 1 (2 )(1143)(300 f) 0.46 hz in heavy load condition the i led and i div is negligible. the heavy load resistance is given by: r heavy v out i out 6.0 v 2.0 a 3.0 the output filter pole at heavy load of this output is f pn 1 (2 r heavy c out ) 1 (2 )(3)(300 f) 177 hz the gain exhibited by the open loop power supply at the high input voltage will be: a v in max v out
2 ns (v in max )(v error )(np)
( 382 v 6.0 v ) 2 (7) (382 v)(1.2 v)(139) 15.53 23.82 db the maximum recommended bandwidth is approximately: f c fs min 5 70 khz 5 14 khz the gain needed by the error amplifier to achieve this bandwidth is calculated at the rated load because that yields the bandwidth condition, which is: gc 20 log f c f ph
a 20 log 14 khz 177
23.82 db 14.14 db the gain in absolute terms is: a c 10 (gc 20) 10 (14.14 20) 51 now the compensation circuit elements can be calculated. the output resistance of the voltage sense divider is given by the parallel combination of resistors in the divider: r in r upper || r lower 10 k || 14 k 5833 r9 (ac) (r in ) 29.75 k 30 k c8 1 2 (a c )(r in )(f c ) 382 pf 390 pf the compensation zero must be placed at or below the light load filter pole: c7 1 2 (r9) (f pn ) 11.63 f 10 f
mc33364 http://onsemi.com 12 r3 47k mc33364 figure 10. critical conduction mode flyback converter the described critical conduction mode flyback converter has the following performance and maximum ratings: output power 12w output 12v @ 1amp max input voltage range 90vac - 270vac j1 line j2 gnd 2 1 1 d1 s380 3 10uf 8 7 1 3 4 2 6 5 gnd vref fb line vcc zcd gate cs 10uf 220 r1 d2 1n4148 21 c4 r4 47k c5 1nf d3 murs160t3 1 r5 2.2 34 q1 mtd1n60 mbrd360 d4 5 4 moc8102 u3 r6 2k7 r7 820 r8 18k 300uf c6 1 23 r9 4k7 100nf c9 u1 u2 j3 j4 1 1 -vout tl431 +vout 9 7 t1 4 2 r2 100k 0.1uf 400v 1 2 converter test data test conditions results line regulation v in = 120vac to 240vac, i out = 0.8a v = 50mv load v in = 120vac, i out = 0.2a to 0.8a v = 40mv v in = 240vac, i out = 0.2a to 0.8a v = 40mv output ripple v in = 120vac, i out = 0.8a v = 290mv v in = 240vac, i out = 0.8a v = 24mv efficiency v in = 120vac, i out = 0.8a = 78.0% v in = 240vac, i out = 0.8a = 79.4% power factor v in = 120vac, i out = 0.8a pf = 0.491 v in = 240vac, i out = 0.8a pf = 0.505 figure 11. load regulation 120v figure 12. load regulation 240v vout iout vout iout ch1: 2.0v/div 2.0 msec/div ch1: 2.0v/div 2.0 msec/div ch2: 200ma/div ch2: 200mv/div
mc33364 http://onsemi.com 13 c3 0.1 m f j1 line d1 b250r c1 f1 t 0.2 a 8 line 7v cc 1 zcd gate 6 cs 2 4 v ref gnd 5 c2 20 m f r1 220 d3 1n4148 r5 47 k r6 47 k c4 1.0 nf q1 mtd1n60e r4 2.2 u1 mc33364d1 54 1 2 j2 543 2 7 9 d6 murs320t3 d7 1n4148 r7 100 d8 b2x84c5v1lt1 c6 1.0 m f r8 4.7 k c5 100 m f u2 mc33341 8 7 6 54 3 2 1 v cc gnd v s csb do cmp cta csa r12 82 k r11 10 k r13 22 k r3 22 k r10 0.25 r9 100 c7 33 nf 3 fb figure 13. universal input battery charger 12 10 m f 400 v t1 d5 murs 160t3 12 5.1 v t1 = 139 turns #28 awg, primary winding 2 - 3 7 turns, bifilar 2 x #26 awg, output winding 9 - 7 19 turns #28 awg, auxiliary winding 4 - 5 on philips ef20-3c85 core gap for a primary inductor of 1.92 mh. output 12 v @ 0.8 amp max input voltage range 90 - 270 vac, 50/60 hz u3 moc8102
mc33364 http://onsemi.com 14 ordering information device package shipping mc33364d1 so8 98 units / rail mc33364d1r2 so8 tape & reel 2500 units / tape & reel mc33364d2 so8 98 units / rail mc33364d2r2 so8 tape & reel 2500 units / tape & reel mc33364d so16 48 units / rail mc33364dr2 so16 tape & reel 2500 units / tape & reel
mc33364 http://onsemi.com 15 package dimensions (so8) d1, d2 suffix plastic package case 75107 issue w seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 x y g m y m 0.25 (0.010) z y m 0.25 (0.010) z s x s m (so16) d suffix plastic package case 751b05 issue j notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimensions a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 18 16 9 seating plane f j m r x 45 g 8 pl p b a m 0.25 (0.010) b s t d k c 16 pl s b m 0.25 (0.010) a s t dim min max min max inches millimeters a 9.80 10.00 0.386 0.393 b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.054 0.068 d 0.35 0.49 0.014 0.019 f 0.40 1.25 0.016 0.049 g 1.27 bsc 0.050 bsc j 0.19 0.25 0.008 0.009 k 0.10 0.25 0.004 0.009 m 0 7 0 7 p 5.80 6.20 0.229 0.244 r 0.25 0.50 0.010 0.019
mc33364 http://onsemi.com 16 on semiconductor and are trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. atypicalo parameters which may be provided in scill c data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including atypicalso must be validated for each customer application by customer's technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body , or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthori zed use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. publication ordering information japan : on semiconductor, japan customer focus center 4321 nishigotanda, shinagawaku, tokyo, japan 1410031 phone : 81357402700 email : r14525@onsemi.com on semiconductor website : http://onsemi.com for additional information, please contact your local sales representative. mc33364/d greenline is a trademark of motorola, inc. literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 3036752175 or 8003443860 toll free usa/canada fax : 3036752176 or 8003443867 toll free usa/canada email : onlit@hibbertco.com n. american technical support : 8002829855 toll free usa/canada

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